1. Field of the Invention
This invention relates to a modulator circuit for a recording system for recording a digital audio signal or a like signal, and more particularly to a demodulator circuit, for example, for a compact disk (CD) recording and reproducing apparatus of the after writing type or the reloadable type in conformity to the compact disk system, which is applied for control of a digital sum variation (DSV) of channel coding.
2. Description of the Prior Art
In recording of a digital audio signal or a like signal, a digital signal is supplied, after an error detection correction code is added thereto, to a modulator circuit, in which it is converted into a code (channel code) suitable for a characteristic of a recording and reproducing system.
FIG. 1A shows an outline of a format of signals of the compact disk system. The 8-14 modulation (hereinafter referred to as EFM) is employed as a modulating system.
According to the EFM, input 8-bit codes (hereinafter referred to as symbols) are individually converted into codes of 14-channel bits, and then a synchronizing signal of 24-channel bits and a sub code of 14-channel bits are added to the 14-channel bit codes, whereafter each adjacent ones of the codes are connected by margin bits of 3-channel bits and then recorded in the NRZI system.
FIG. 1B shows construction of a frame of the CD system. Referring to FIG. 1B, in the period of one synchronization frame (a section of 6 sample values, each 6 samples for L- and R-channels, one sample consists of 16 bit data), data of 24 symbols and a parity of 8 symbols inputted from a CIRC (cross interleave Reed Solomon code) encoder to a modulator circuit are individually converted into 14-channel bits, each adjacent ones of which are connected by margin bits of 3-channel bits to make up 588-channel bits for one frame as shown in FIG. 1B. The 588-channel bits are NRZI recorded at the channel bit rate of 4.3218 Mbps onto a compact disk.
Here, each symbol inputted to the modulator circuit is converted, for example, by referring to a lookup table ROM, into a channel bit pattern wherein the number of "0" between "1" and "1" is equal to or greater than 2 but equal to or less than 10. Meanwhile, the channel bit pattern of the frame synchronizing signal Sf is "100000000001000000000010", and each margin bit pattern is selected from among "000", "001", "010" and "100". Further, one sub coding frame is constituted from 98 frames, and sub code synchronizing signals S.sub.0 (="001000000000001" and S.sub.1 (="00000000010010" are added as sub codes for the 0th and first frames, respectively (refer to FIG. 1C).
FIG. 2 shows channel bit patterns and a DSV (digital sum variation) after EFM of a certain sample value. Referring to FIG. 2, one sample of 16 bits is divided into upper 8 bits and lower 8 bits and is inputted by way of a CIRC encoder into a modulator circuit, in which it is 8-14 modulated into information bits. As described above, two or more but ten or less "0"s are present between "1" and "1" of the information bits. One of "000", "001", "010" and "100" is selected as margin bits such that the rule always applies to a location at which adjacent information bits are connected. Thus, an EFM signal which includes a unit of 17-channel bits (except the frame synchronizing signal Sf which includes 27-channel bits) is outputted at 4.3218 Mbps from the modulator circuit.
Since two or more but ten or less channel bits of "0" are present between an arbitrary channel bit "1" and a next channel bit "1" in this manner, the continuing period (recording wavelength) of the high level or the low level of a NRZI recording waveform is equal to or greater than 3T but equal to or less than 11T without fail (refer to FIG. 2). In other words, in this instance, the minimum recording wavelength is 3T and the maximum recording wavelength is 11T. This will be hereinafter referred to as EFM 3T to 11T rule. Here, T is one period of the channel clocks 4.3218 MHz.
As an index to a DC balance of a NRZI recording waveform, a digital sum variation (DSV) is considered here. A DSV is given as a time integration of a recording waveform. In particular, a variation of the DSV when the high level of a recording waveform continues for a unit time T is defined as +1, and another variation of the DSV when the low level continues for the unit time T is defined as -1.
A variation of a DSV with respect to time when it is assumed that the initial value of the DSV at the time t.sub.0 is equal to 0 is shown at the lowermost stage of FIG. 2. Here, a modulation signal for the period from t.sub.1 to t.sub.2 does not decisively depend upon the 17-channel bit pattern "01000001000001001", but depends upon the level of the demodulation signal at the time t.sub.1, in short, upon the last level (hereinafter referred to as CWLL) of the modulation signal waveform for the period from t.sub.0 to t.sub.1. Accordingly, the modulation signal waveform shown in FIG. 2 is a modulation signal waveform when the CWLL is at the low level (CWLL="0") at the time t.sub.0, and the modulation signal waveform when the CWLL is CWLL="1" (high level) at the time t.sub.0 presents an opposite pattern in which the high level and the low level are replaced from those of the former pattern. Similarly, an increase or a decrease of the DSV depends upon the CWLL, and when the CWLL is CWLL="0" at the time t.sub.0, the variation of the DSV by the information bit pattern "01000100100010" (such variation will be hereinafter referred to as 14NWD), in short, the variation of the DSV for the period from t.sub.0 to t.sub.0+14), is +2 as seen from FIG. 2. If the CWLL is CWLL="1" at the time t.sub.0 contrary to the illustration of FIG. 2, then the 14NWD is 14NWD=-2. Further, a variation of the DSV for the period from t.sub.0+14 to t.sub.1+14 is hereinafter referred to as 17NWD.
Margin bits to be inserted in the period between t.sub.0+14 and t.sub.1 will be describes subsequently.
Of the four kinds or patterns of margin bits "000", "001", "010" and "100", the margin bit patterns "001" and "100" cannot be inserted in accordance with the EFM 3T to 11T rule, but the margin bit patterns "010" or "000" can be inserted. In particular, if the quantity of "0" at the rear end of the preceding information bit pattern outputted prior to the margin bits is presented by B and the quantity of 0 at the front end of the present information bit pattern to be outputted subsequently is represented by A, then since B=1 and A=1, the front end of the margin bit pattern to be inserted must be "0" and the last end of the margin bit pattern must be "0", and accordingly, the margin bit pattern which can be inserted is "0.times.0".
The DSV when "010" is inserted as the margin bit pattern is indicated by a solid line while the DSV when "000" are inserted is indicated by a broken line in FIG. 2.
When addition of two of more of the four margin bit patterns is available, one of the available margin bit patterns is selected so that the DSV may be minimized with the 14NWD of the present information bits. In particular, since the DSV at the time t.sub.1+14 is +3 with the margin bit pattern of "010" and -1 with the margin bit pattern of "000", the margin bit pattern "000" is selected as an optimum margin bit pattern and the margin bits "000" are added in the period between t.sub.0+14 and t.sub.1.
As described above, a margin bit pattern or patterns are first selected so that they may satisfy the EFM 3T to 11T rule at a connecting point between the information bit patterns, and then if a plurality of margin bit patterns can be inserted, then such a margin bit pattern is selected as will cause the DSV to approach zero most among them.
FIG. 3 is a block diagram of a modulator circuit disclosed in Japanese Patent Laid-Open Application No. 1-319178. Referring to FIG. 3, the modulator circuit shown has an input terminal 101 for receiving symbols from a CIRC encoder not shown, another input terminal 102 for receiving system clocks Sc of 4.3218 MHz, a further input terminal 103 for receiving a frame synchronizing timing signal, and a still further input terminal 104 for receiving a synchronizing timing signal for a sub coding frame.
Symbols successively inputted to the input terminal 101 are each 8-14 modulated by a ROM 111 and stored into a register 112, and two 4-bit data A and B representative of the numbers of "0" at the front end and the rear end of each 14 bit data are stored into the register 112.
At a synchronization timing of each frame and a synchronization timing of a sub coding frame, a false frame synchronizing signal S'f and sub coding frame synchronizing signals S.sub.0 and S.sub.1 are individually outputted as 14-bit data from a ROM 116 under the control of a system controlling circuit 115 and stored into the register 112. Here, the 14-bit false frame synchronizing signal S'f (=100000000001000" is temporarily determined as a frame synchronizing signal Sf of 24 bits, and this is converted, upon outputting, into a frame synchronizing signal Sf of 24 bits. Further, two 4-bit data A and B representative of the numbers of "0" at the front end and the rear end of the synchronizing signals S'f, S0 and S1 are stored into the register 112.
The 14 bit data stored in the register 112 are successively transferred to registers 113 and 114. Consequently, the last 14-bit data are stored in the register 113, and the second last 14-bit data are stored in the register 114. The 4-bit data A are supplied from the register 112 to a pair of ROMS 117 and 118, and the 4-bit data B are transferred from the register 112 to the register 113. Consequently, the last 4-bit data B are supplied from the resister 113 to the ROMs 117 and 118.
The ROM 117 receives the 4-bit data A and the last 4-bit data B as address input data and outputs a margin bit pattern which satisfies the EFM 3T to 11T rule to a selector 120. In the case of an exceptional combination (11 combinations are possible) which does not violate the EFM 3T to 11T rule but will result in production, in a bit pattern produced by connection of the margin bits, of a bit pattern same as the 24-bit frame synchronizing signal Sf, the ROM 18 outputs another margin bit pattern which is limited particularly so that such a combination may not occur. In other words, the ROM 118 outputs a margin bit pattern upon occurrence of an exceptional violation of the rule to the selector 120.
A detecting circuit 119 refers to the three 14-bit data stored in the registers 112, 113 and 114 and the last margin bits stored in a register 142 to detect occurrence of an exceptional combination described above and changes over read-out of margin bits from the ROM 117 to the ROM 118. Margin bits outputted from the ROM 117 or the ROM 118 are inputted as an address to a ROM 122 by way of the selector 120. Meanwhile, the 14-bit data are inputted as an address from the register 112 to the ROM 123.
The ROM 122 outputs a DSV corresponding to the margin bits inputted thereto and a polarity of the DSV, and the DSV is stored into a DSV register 125 while the polarity is stored into a polarity register 127. Meanwhile, the ROM 123 outputs a DSV corresponding to the 14-bit data inputted thereto and a polarity of the DSV, and the DSV is stored into a DSV register 124 and the polarity is stored into a polarity register 126.
The pattern of the margin bits outputted from the ROM 117 or 118 is one of four margin bit patterns (each hereinafter referred to as first, second, third or fourth margin bits or bit pattern) to the utmost, but in order to assure the unification of processing, always the margin bits of the four margin bit patterns are outputted. An optimum margin bit pattern among them is determined in the following manner.